1. Field of the Invention
The present invention relates to sequential storage circuitry for an integrated circuit.
2. Description of the Prior Art
As device geometries shrink (for example there is currently much development in the area of sub-45 nm technology design), this has pushed existing CMOS materials much closer to their intrinsic reliability limits. The stress observed in the devices at these reduced geometries causes them to age faster, which reduces the life of such devices. Many articles have been written concerning this reliability problem, see for example the article “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation”, by S Borkar, IEEE Micro November-December 2005, and the article “Reliability Challenges for 45 nm and Beyond” by J McPherson, IEEE Design Automation Conference (DAC), 2006. The reliability problem is often touted as one of the most important concern for future devices.
One of the major causes of an unreliable device is NBTI (Negative Bias Temperature Instability), as for example is discussed in the article “The Impact of NBTI on the Performance of Combinational and Sequential Circuits”, by W Wang et al, IEEE Design Automation Conference (DAC), 2007. NBTI is an effect that primarily affects the PMOS devices, causing them to become stressed at higher temperature when the gate-source bias is negative. The usual impact of NBTI is an increase in the device threshold (Vt) over the life of the device, which slows the operation of the device down as it ages with use. Hence, the degradation of device threshold can manifest as path delay failures in the device. However, the shift in Vt is a function of the stress level on the device. A PMOS device which has a static logic “0” value at its gate and a static logic “1” value at its source is likely to get much more stressed than an equivalent PMOS device where the inputs (hence gate-source bias) change with time. The changing bias anneals the stress and hence it does not let the Vt degrade. A similar but reverse phenomenon happens for metal gate, high-k dielectric transistors. In this case, PBTI (Positive Bias Temperature Instability) stress impacts the NMOS devices in the design.
The NBTI and PBTI phenomena are not as much of a problem for any high activity domains of a chip because the stress gets annealed due to the bias changes that naturally occur in such high activity domains. However, any low activity domains are under much more stress due to almost static bias. If the static stress remains for a substantially long time, even a subsequent change in bias cannot recover the Vt degradation.
A common technique to design around this problem is to over-design and increase the margins of a device such that, over the lifetime of the device, the design is not affected by slow down. Such techniques are described, for example, in the article “Combating NBTI Degradation via Gate Sizing” by X Yang et al, IEEE International Symposium on Quality Electronic Design (ISQED), 2007, and the article “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design”, by R Vattikonda et al, IEEE Design Automation Conference (DAC), 2006. Over-design with margins has become very expensive due to stringent area, performance and power demands for nanometer designs. The following are the common standard techniques (and their drawbacks) to reduce Vt degradation due to NBTI:                Vdd and Vt tuning: This involves determining an optimal value of Vdd/Vt ratio to minimize Vt degradation. However, every gate has a different optimal ratio and it is not possible to have an independent supply for every gate.        Gate sizing: This involves increasing the device size and over-design. However, as mentioned earlier, this has significant costs in terms of area and power.        Stack effect: This involves replacing a transistor with two or more transistors in series (a “stack”), which increases Vt due to the body effect. This hence reduces the effect of Vt degradation over time due to NBTI, but with a performance cost resulting from the use of stacked transistors.        Duty cycle control: This involves reducing the proportion of time that the gate of a PMOS device is at a logic “0” voltage level, which can reduce Vt degradation due to NBTI. However, such a step has a significant impact on other aspects of the architectural design of the system using such PMOS devices.        
All of the techniques mentioned above are expensive to implement, either due to area increase, power increase, increase in complexity of the overall system design, or a combination of these factors.
In the area of SRAM memory, the article “Impact of NBTI on SRAM Read Stability and Design for Reliability”, by S Kumar et al, Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), 2006, describes a technique for reducing NBTI related stress in SRAM memory cells by causing the bits stored in an array of SRAM cells to be flipped occasionally. When a flip control signal is asserted, data is read from each SRAM cell in the array, flipped and stored back to the same cell, the process being performed for all SRAM cells in the array. This process is performed at a time when the processor associated with the SRAM array is in stand-by mode, thereby ensuring processor operation is not affected. Following such a procedure, a modified read and write mechanism is used when accessing the SRAM array to take account of the fact that the data has been flipped.
It is relatively easy to implement this method for SRAM arrays due to regular and localized design. The same technique cannot be used for sequential storage circuitry such as flip-flops and latches, or for the combinatorial circuitry interposed between such sequential storage circuitry, due to their spatial distributions on chip.
It would be desirable to develop a design of sequential storage circuitry which enabled mitigation of stress build up, whilst alleviating the power, area and complexity issues associated with the known prior art techniques.